1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a thin film transistor (TFT) array substrate and a method of manufacturing the same.
2. Discussion of the Related Art
A liquid crystal display device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Liquid crystal molecules have a definite orientational alignment as a result of their long, thin shapes. That orientational alignment can be controlled by an applied electric field. In other words, as an applied electric field changes, so does the alignment of the liquid crystal molecules. Due to the optical anisotropy, the refraction of incident light depends on the orientational alignment of the liquid crystal molecules. Thus, by properly controlling an applied electric field a desired light image can be produced.
A liquid crystal is classified into a positive liquid crystal and a negative liquid crystal, in view of an electrical property. The positive liquid crystal has a positive dielectric anisotropy such that long axes of liquid crystal molecules are aligned parallel with an electric field. Whereas, the negative liquid crystal has a negative dielectric anisotropy such that long axes of liquid crystal molecules are aligned perpendicular to an electric field.
While various types of liquid crystal display devices are known, active matrix LCDs having thin film transistors and pixel electrodes arranged in a matrix are probably the most common. This is because such active matrix LCDs can produce high quality images at reasonable cost.
FIG. 1 shows the configuration of a typical TFT-LCD device. The TFT-LCD device 11 includes upper and lower substrates 5 and 22 with an interposed liquid crystal 14. The upper and lower substrates 5 and 22 are called a color filter substrate and an array substrate, respectively.
In the upper substrate 5, on a surface opposing the lower substrate 22, black matrix 6 and color filter layer 7 that includes a plurality of red (R), green (G), and blue (B) color filters are formed in shape of an array matrix such that each color filter 7 is surrounded by the black matrix 6. Further on the upper substrate 5, a common electrode 18 is formed and covers the color filter layer 7 and the black matrix 6.
In the lower substrate 22, on a surface opposing the upper substrate 5, thin film transistors (TFTs) “T”, as switching devices, are formed in the shape of an array matrix corresponding to the color filter layer 7, and a plurality of crossing gate and data lines 13 and 15 are positioned such that each TFT “T” is located near each crossover point of the gate and data lines 13 and 15. Further in the lower substrate 22, a plurality of pixel electrodes 17 are formed on an area defined by the gate and data lines 13 and 15. The area there defined is called a pixel region “P”. The pixel electrode 17 is usually formed from a transparent conductive material having good transmissivity, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
The pixel and common electrodes 17 and 18 generate electric fields that control the light passing through the liquid crystal cells. By controlling the electric fields desired characters or images are displayed.
To complete the array substrate described above, a depositing technique, a photolithography technique, and an etching technique are repeated several times. Namely, a typical TFT array substrate manufacturing process requires repeated steps of depositing and patterning various layers. The patterning steps involve photolithography masks. Each photolithography step is facilitated using one mask, and the number of masks used in the fabrication process is a critical factor in determining the number of patterning steps. Thus, the production cost depends heavily on the number of masks used in the manufacturing process. Moreover, the margin of error caused by a plurality of manufacturing processes depends heavily on the number of masks, and thus, the ratio of inferior goods is also lowered if the number of the mask is lowered.
Accordingly, the TFT array substrate, nowadays, tends to be fabricated using four mask processes instead of five mask processes. However, when using the four mask processes, a plurality of layers that are stacked upon each other are simultaneously etched. Also, the etching ratios of the different layers should be adjusted during the etching process. As a result, some portions of the lines, such as the gate and data lines, become exposed and some portions of the electrodes, such as the source, drain and gate electrodes, are also exposed. Above all, since the gate line and the gate electrode are usually formed of a low-resistance material when fabricating the TFT array substrate using the four mask processes, the exposed low-resistance material is gradually eroded by the etchant during the manufacturing processes.
Now, referring to the attached drawings, the erosion of the gate line and gate electrode will be explained in detail hereinafter.
FIG. 2 is a schematic partial plan view showing pixels of the TFT array substrate that is fabricated using four mask processes. As shown, the TFT array substrate includes a gate line 13 formed on a transparent substrate, a data line 15 perpendicularly crossing the gate line 13, a TFT “T” formed at regions near the crossover point of the gate and data lines 13 and 15, and a pixel electrode 17 connected to the TFT. A pixel region where the pixel electrode 17 is positioned is defined by the gate and data electrodes 13 and 15.
Still referring to FIG. 2, the TFT “T” is comprised of a gate electrode 31, a source electrode 33 and a drain electrode 35. The gate electrode 31 is extended from the gate line 13 and the source electrode 33 is extended from the data line 13. Further, the drain electrode 35 is spaced apart from the source electrode 33 and a channel region “CH” is formed between the source and drain electrodes 33 and 35. The gate electrode 31 and gate line 13 are formed using a first mask. The data line 15 and source and drain electrodes 33 and 35 are formed using a second mask. Also, the pixel electrode 17 is formed using a fourth mask. In the case of forming the TFT array substrate using the four mask processes, an active layer 37 is not formed independently using another patterning process. Namely, the active layer 37 is simultaneously formed when a protection layer 41 is patterned using a third mask, and thus, the active layer are located along and under the data line 15, source electrode 33 and drain electrode 35.
However, during the third mask process that patterns the protection layer 41, portions “B” and “C” of the gate electrode 31 are exposed. Thereafter, these exposed portions “B” and “C” of the gate electrode 31 are eroded by the stripper that removes the photo resist and by the etchant that removes a metallic layer during the fourth mask process.
For further explanation, a manufacturing process of the TFT array substrate is explained referring to FIG. 3A to 3D.
FIGS. 3A to 3D are plan views and FIGS. 4–11 are corresponding cross-sectional views that relate to lines III—III and IV—IV of related art FIG. 2, and illustrate a process for manufacturing a related art TFT array substrate for use in the liquid crystal display device.
FIGS. 3A, 4 and 5 show a first mask process. As shown, a first metal layer, for example copper (Cu), is deposited on a substrate 22, and then patterned so as to form the gate line 13 and gate electrode 31 using a first mask. After that, a gate insulation layer 32, an amorphous silicon layer 34, an impurity-included amorphous silicon layer 36, and a second metal layer 38 are deposited in series on a surface of the substrate 22 having the gate line 13 and gate electrode 31.
FIGS. 3B, 6 and 7 show a second mask process. As shown, the second metal layer 38 of FIGS. 4 and 5 is patterned so as to form the data line 15, the source electrode 33 and the drain electrode 35. Again, the data line 15 is perpendicular to the gate line 13 and the source electrode 33 is extended from the data line 15 over the pixel region “P” of FIG. 2. Also, the drain electrode 35 formed in the pixel region is spaced apart from the source electrode 33.
Next, the impurity-included amorphous silicon layer 36 of FIGS. 4 and 5 is patterned using the patterned second metal layer as masks. Thus, an ohmic contact layer 39 is formed under the patterned second metal layer such as the data line 15 and the source and drain electrodes 33 and 35. Moreover, a portion of the amorphous silicon layer 34 between the source and drain electrodes 33 and 35 is exposed so as to form the channel region “CH”.
FIGS. 3C, 8 and 9 show a third mask process. The protection layer 41 is deposited on the amorphous silicon layer 34 of FIGS. 6 and 7 and on the patterned second metal layer. After that, a drain contact hole 43 is formed by patterning the protection layer 41. At this time, the protection layer 41 is mostly removed except portions that protect the data line 15, channel region “CH” and source and drain electrodes 33 and 35. Also, the amorphous silicon layer 34 of FIGS. 6 and 7 and the gate insulation layer 32 are simultaneously removed except the portions under the channel region “CH” and under the patterned second metal layer (i.e., the data line 15 and the source and drain electrodes 33 and 35). Thus, under the patterned protection layer 41, the active layer 37 is formed. Further, in this structure of the TFT, since this active layer 37 does not cover the whole gate electrode 31 in order to form the channel region “CH”, the protection layer 41 and the active layer 37 exist between the source electrode 33 and the drain electrode 35.
As a result, since the channel region “CH” is formed between the source and drain electrodes 33 and 35, the portions “B” and “C” of the gate electrode 31 are exposed after performing this third mask process. Moreover, the gate line 13 is also exposed.
FIGS. 3D, 10 and 11 show a fourth mask process. A transparent conductive material, such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), is deposited on the surfaces of the above-mentioned intermediates. Thereafter, the transparent conductive material is patterned to form the pixel electrode 17 that is electrically connected with the drain electrode 35 through the drain contact hole 43.
As described above, after performing the third mask process, the exposed gate electrode portions “B” and “C” and the gate line 13 are eroded and damaged during the fourth mask process. Namely, when forming the pixel electrode 17, the exposed gate line 13 and gate electrode portions “B” and “C” are eroded and damaged by the etchant that etches the transparent conductive material. Subsequently, when removing the photo resist that is formed for the pixel electrode 17, the exposed gate line 13 and gate electrode portions “B” and “C” are secondly eroded and damaged by the stripper.
Further, if the gate line and the gate electrode are made of copper (Cu), the copper ions are diffused into the liquid crystal layer after the liquid crystal panel is complete. Thus, the liquid crystal display device malfunctions due to the diffused copper ions.